Objective: Design a Clock Divider to divide the input clock by 3.<hr>A clock divider is used to reduce the frequency of an input clock signal <code>clk</code> by a specific factor. In this case, we want to divide the input clock frequency by 3, which effectively generates an output clock signal <code>clk_out</code> with one-third the frequency of the input. To achieve a division by 3, you need to create logic that generates a pulse <code>clk_out</code>for every third rising edge of the input clock <code>clk</code>. Use an active high reset signal <code>reset</code> in the design.<hr>Module instantiation to follow :&nbsp;<ul><li>Module : <code>clk_div3</code></li><li>Inputs:<ul><li><code>reset</code> : 1-bit active high reset input</li><li><code>clk</code> : 1-bit Clock input</li></ul></li><li>Outputs:<ul><li><code>clk_out</code>: 1-bit divided clock output</li></ul></li></ul>

Clock Divider by 3